ANTIC, GTIA and timing info

First the links to the chip info: ANTIC, GTIA.

Note: Most of this info was gathered/tested on PAL equipment. There may be significant differences on NTSC systems. I'll try to note where are the main diffs.

How is the video generated

ANTIC does all the screen processing for programmer (unlike 2600, where programmer had to push all the graphics info on the fly to the TIA). It takes the playfield data, player missile data (PMG), display list data from the main bus on the speed of the cpu using DMA. For each byte ANTIC reads from the bus causes main CPU to stop - this is called cycle stealing. ANTIC also does the DRAM refresh, this is also performed as a DMA task and steals the cycles too.

The playfield data is then sent to GTIA on three bit ANx bus on the double speed. GTIA colors the bits, adds PM graphics, evaluates the collisions and outputs some analog data (sync and color info) and some digital data (luminance info).

Important terms

Vertical events description

Scanlines, from the top of the screen:
278TODOreset VSYNC
8TODOstart of display
248TODOstart of VBLANK

Horizontal events description

Color clocks, from the left of the screen, same for PAL/NTSC:
0Start HSYNC
32End HBLANK & Start wide
34Start display
44Start displayed wide
48Start normal & start HSCROL
64Start narrow
192End narrow
208End WSYNC & end normal
220End displayed wide
222Start HBLANK & inc VCOUNT & end display
224End wide

Cycle counting - DLIST

Each byte of display list takes one cycle. First byte is taken on cclock 0, two optional ones on cclocks 10 & 12.

Cycle counting - PMG

Missile takes one byte on scanline (cclock 226). Players take 4 cycles on scanline (cclocks 2-8). It doesn't matter if one or two lines resolution is on, DMA is done on every line anyway. If player DMA is on, missile DMA is turned on automatically. There's 240 cycles per frame taken. GTIA 'knows' (probably from ANx bus communication) when the scanline begins, so it counts the cycles and then grabs the content of the data bus for PMG data. If GRACTL is 'on' but PMG DMA is off, the flickering happens, that is nothing else but the content of the data bus (which looks random).

Cycle counting - refresh

On most lines, 9 cycles of refresh are taken. Only in hires text modes the refresh cycles are preempted by the playfield dma, so only 1 refresh cycle occurs, with the exception of narrow mode, where 2 refresh cycles occur.

Cycle counting - playfield

For graphics modes, all bytes are fetched on first line once and then repeated on succeding lines.

For text modes, on first scanline the character codes and graphics data are fetched, on succeding lines only the graphics data are fetched.

Cycle counting - VSCROL


Cycle counting - HSCROL


Cycle counting - example

Graphics 0 screen:

Type Cycles
Characters40 * 24960
PF40 * 24 * 87680
REF312 * 9 - 8 * 242616
Total DMA 11288
Total free 24280
Total cycles312 * 11435568

See the attached picture for better info: gr.0 (15 KB PNG)

ANTIC modes


ANx bus

010HBLANK & reset hi-res
011HBLANK & set hi-res

In hi-res graphics modes are 1xx states understood as 2 pixels.
In GTIA modes, 1xx states are halves of pixes, first left, then right one. . Back (c) 1998-2004 Jindroush Last modified: Wed Apr 28 22:02:44 2004